`include "timescale.v"

module onu_mux(
	// input  [8:0]   tx_fifo_bus, report_bus, register_req_bus, register_ack_bus,
	input  [8:0]   tx_fifo_bus, tx_mpcp_bus,
	
	input     	   sel,	
	output 	   	   h_tx_data_ready,
	output [7:0]   h_tx_data
	);

// assign 			  {h_tx_data_ready, h_tx_data} = tx_fifo_bus;

assign {h_tx_data_ready, h_tx_data} = sel ? tx_mpcp_bus : tx_fifo_bus;
// always@(*)
// begin
//   if(sel==2'b00)
// 	{h_tx_data_ready, h_tx_data} = tx_fifo_bus;
//   else if(sel==2'b01)
// 	{h_tx_data_ready, h_tx_data} = report_bus;
//   else if(sel==2'b10)
// 	{h_tx_data_ready, h_tx_data} = register_req_bus;
//   else if(sel==2'b11)
// 	{h_tx_data_ready, h_tx_data} = register_ack_bus;
//   else
// 	{h_tx_data_ready, h_tx_data} = 9'hx;
// end

endmodule // onu_mux
